Semiconductor device and method for producing the same

ABSTRACT

Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application based upon U.S. patent application Ser.No. 13/785,674, filed Mar. 5, 2013 and claims the benefit of priorityfrom Japanese Patent Application No. 2012-054170 filed on Mar. 12, 2012the disclosure of which is incorporated herein in its entirely byreference.

BACKGROUND

The present invention relates to a semiconductor device, and a methodfor producing the device, in particular, a technique that can be usedsuitably for a semiconductor device having a high-breakdown-voltagetransistor.

For example, a MOSFET (metal oxide semiconductor field effecttransistor) used in the state that a high voltage of several tens ofvolts is applied to a drain region thereof is disclosed in JapaneseUnexamined Patent Application Publication (JP-A) No. 2008-4649 (PatentDocument 1). According to this publication, a buried layer is formedbetween a semiconductor substrate and a semiconductor layer over thesubstrate. In order that the buried layer can restrain the action of aparasitic bipolar transistor generated in the vertical direction (in theupper and lower direction), the concentration of a dopant (impurity) inthe buried layer, which corresponds to the base of the parasitictransistor, is made sufficiently large.

PRIOR DOCUMENT Patent Document

[Patent Document 1] Japanese Unexamined Patent Application PublicationNo. 2008-4649

SUMMARY

However, it is necessary to use a single photomask (working mask) forforming the buried layer other than a photomask for forming the otherregions. Moreover, the semiconductor layer is formed by epitaxialgrowth; thus, costs may be increased through the steps making use of thephotomask and the epitaxial growth. It is therefore an object of theinvention to reduce costs when a high-breakdown-voltage MOSFET isproduced while the action of a parasitic bipolar transistor isrestrained.

Other objects and new features of the present invention will be madeevident from the description of the present specification, and theattached drawings.

According to a first aspect of the invention, a high-breakdown-voltagep-channel-type transistor included in a semiconductor device has a firstn-type semiconductor layer arranged in a semiconductor substrate and ata main-surface-side (upside) of a p-type region (in the semiconductorsubstrate), and a local n-type buried region arranged, just below afirst p-type dopant region from which a drain region is taken out, tocontact the first n-type semiconductor layer.

According to a second aspect of the invention, a method for producing asemiconductor device having a high-breakdown-voltage p-channel-typetransistor includes: forming a first n-type semiconductor layer insidethe semiconductor substrate and at the main-surface-side (upside) of ap-type region in the semiconductor substrate; and forming a local n-typeburied region, just below a first p-type dopant region from which adrain region is taken out, to contact the first n-type semiconductorlayer. The same mask is used to conduct the step of forming the firstp-type dopant region and the step of forming the local n-type buriedregion.

According to the first aspect, the local n-type buried region increasesthe thickness of a region corresponding to the base of a parasitebipolar transistor to make it possible to promote an advantageous effectof restraining the action of the parasite bipolar transistor.

According to the second aspect, it becomes unnecessary to use anadditional photomask for forming the local n-type buried layer. Thus,production costs for the semiconductor device can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic plan view of a semiconductor device according tofirst embodiment of the present invention.

FIG. 2 is a schematic sectional view illustrating the configuration andthe structure of MOSFETs in a region where a high-breakdown-voltageanalogue I/O circuit in FIG. 1 is formed in first embodiment.

FIG. 3 is a schematic plan view illustrating a portion of the structureof a region represented by “III” in FIG. 2, this portion being a portionwherein a p-type dopant region PR as a first p-type dopant region isexcluded from the structure.

FIG. 4 is a concentration profile graph showing the respectiveconcentrations of dopants in a region represented by “IV” in FIG. 2.

FIG. 5 is a schematic sectional view illustrating the region illustratedby FIG. 2 in a first step in a producing method according to firstembodiment.

FIG. 6 is a schematic sectional view illustrating the region illustratedby FIG. 2 in a second step in the producing method according to firstembodiment.

FIG. 7 is a schematic sectional view illustrating the region illustratedby FIG. 2 in a third step in the producing method according to firstembodiment.

FIG. 8 is a schematic sectional view illustrating the region illustratedby FIG. 2 in a fourth step in the producing method according to firstembodiment.

FIG. 9 is a schematic sectional view illustrating the region illustratedby FIG. 2 in a fifth step in the producing method according to firstembodiment.

FIG. 10 is a schematic sectional view illustrating the regionillustrated by FIG. 2 in a sixth step in the producing method accordingto first embodiment.

FIG. 11 is a schematic sectional view illustrating the regionillustrated by FIG. 2 in a seventh step in the producing methodaccording to first embodiment.

FIG. 12 is a schematic sectional view illustrating the regionillustrated by FIG. 2 in an eighth step in the producing methodaccording to first embodiment.

FIG. 13 is a schematic sectional view illustrating the regionillustrated by FIG. 2 in a ninth step in the producing method accordingto first embodiment.

FIG. 14 is a schematic sectional view illustrating the regionillustrated by FIG. 2 in a tenth step in the producing method accordingto first embodiment.

FIG. 15 is a schematic sectional view illustrating the configuration andthe structure of MOSFETs in a region where a high-breakdown-voltageanalogue I/O circuit is formed in a technique related to firstembodiment.

FIG. 16A is a graph showing a relationship between ion implantationenergy for forming a local n-type buried region, and the substrateleakage current proportion and breakdown voltage (corresponding to theenergy).

FIG. 16B is a graph showing a relationship between ion implantationdosage for forming the local n-type buried region, and the substrateleakage current proportion and breakdown voltage (corresponding to thedosage).

FIG. 17 is a schematic sectional view illustrating the configuration andthe structure of MOSFETs in a region where a high-breakdown-voltageanalogue I/O circuit is formed in third embodiment of the invention.

FIG. 18 is a schematic sectional view illustrating the configuration andthe structure of MOSFETs in a region where a high-breakdown-voltageanalogue I/O circuit is formed in fourth embodiment of the invention.

DETAILED DESCRIPTION

Hereinafter, embodiments of the invention will be described withreference to the drawings.

First Embodiment

First, with reference to FIG. 1, a description will be made about theconfiguration of individual element-formed regions in a main surface ofa semiconductor substrate SUB of a semiconductor device DEV according tofirst embodiment of the invention.

As illustrated in FIG. 1, the semiconductor device DEV of the presentembodiment has, in the main surface of the semiconductor substrate SUB,for example, regions in each of which a high-breakdown-voltage analogueI/O circuit is formed, a region where a low-voltage logic circuit isformed, a region where a low-voltage analogue circuit is formed, and aregion where the so-called SRAM (static random access memory) is formed.

The high-breakdown-voltage analogue I/O circuits are each a circuitusable in the state that a driving voltage higher than ordinarily usedvoltages is applied to this circuit, and usable in order to input andoutput electrical signals between this circuit, and a power supplycircuit as well as the low-voltage logic circuit and others. Thelow-voltage logic circuit is a circuit having a control circuit, forexample, a logic circuit composed of plural MIS transistors or others inorder to make arithmetic calculations, using digital signals. Thelow-voltage analogue circuit is a circuit driven by effect of a lowvoltage equivalent to the voltage for the low-voltage logic circuit.However, this circuit is a circuit for making arithmetic calculations,using analogue signals. The SRAM includes plural MIS transistors, and isused as an element for memorizing data inside the present semiconductordevice. The semiconductor device also has, for example, a region wherethe power supply circuit is formed, which is not illustrated in FIG. 1.The power supply circuit is a circuit for supplying a supply voltage fordriving each of the above-mentioned circuits.

FIG. 2 is a schematic sectional view of a region taken along line II-IIin FIG. 1. The analogue I/O circuits in FIG. 1 each have, for example,the so-called high-breakdown-voltage pMOSFET (high-breakdown-voltagep-channel type transistor) as illustrated in the sectional view of FIG.2. The high-breakdown-voltage pMOSFET denotes a p-channel type MOStransistor having a breakdown-voltage performance against a high drainvoltage of, for example, 10 V or more.

As illustrated in FIG. 2, the region where each of thehigh-breakdown-voltage analogue I/O circuits in FIG. 1 is formed has notonly the above-mentioned pMOSFET but also a high-breakdown-voltagenMOSFET (high-breakdown-voltage n-channel-type transistor). Insubstantially the same manner as the high-breakdown-voltage pMOSFET, thehigh-breakdown-voltage nMOSFET denotes an n-channel-type MOS transistorhaving a breakdown-voltage performance against a high drain voltage of,for example, 10 V or more.

The high-breakdown-voltage pMOSFET mainly has an n-type buried layer NI(first n-type semiconductor layer), a local n-type buried region RBN, ann-type well region LNW, a p-type drift layer HPDF for high breakdownvoltage, an n-type dopant region NR, p-type dopant regions PR, gateelectrons G, and an element isolation insulating film LS. These areformed in the semiconductor substrate SUB, which is made of, forexample, silicon monocrystal and has a p-type region PSR containing ap-type dopant. As illustrated in FIG. 3, these individual regions areextended basically in a direction perpendicular to surfaces of the paperon which FIG. 2 is drawn.

The p-type region PSR is a dopant region where ions of a p-type dopant,such as boron, are introduced into the silicon monocrystal. The n-typeburied layer NI is a dopant region arranged to be buried in thesemiconductor substrate SUB and containing ions of an n-type dopant,such as phosphorous. The n-type buried layer NI is arranged at the mainsurface side of the semiconductor substrate SUB (that is, over thep-type region PSR), this main surface being represented by MS, whenviewed from the p-type region PSR. The n-type buried layer NI isarranged, for example, to contact the upper side of the p-type regionPSR. The n-type buried layer NI is an n-type semiconductor layer forattaining, inside the semiconductor substrate SUB, electrical isolationof the p-type region PSR from the p-type dopant regions (such as thep-type drift layer HPDF for high breakdown voltage) at the semiconductorsubstrate SUB main surface MS side of the p-type region PSR.

In the same manner as introduced into the p-type region PSR, p-typedopant ions are introduced into central one out of the p-type dopantregions PR, as well as into the high-breakdown-voltage p-type driftlayer HPDF. The p-type dopant region PR, and the high-breakdown-voltagep-type drift layer HPDF formed to surround the region PR are each aregion (first p-type dopant region) formed in the main surface MS of thesemiconductor substrate SUB in order to take out a drain electrode D. Itis preferred that the p-type dopant in the p-type drift layer HPDF ishigher in concentration than the p-type dopant in the p-type region PSRand is lower in concentration than the p-type dopant in the p-typedopant region PR surrounded by the p-type drift layer HPDF (in order totake out the drain electrode D).

The high-breakdown-voltage p-type drift layer HPDF is a region formed inthe main surface MS in order to attain a smoother electric connectionbetween the p-type dopant region PR surrounded by the layer HPDF, andthe p-type region PSR. Even if a high voltage is applied to the drainelectrode D, the arrangement of the high-breakdown-voltage p-type driftlayer HPDF makes it possible to restrain the generation ofinconveniences following a matter that an electric field becomesextremely high in the high-breakdown-voltage p-type drift layer HPDF andthe vicinity thereof.

In the main surface MS of the semiconductor substrate SUB, the other ofthe p-type dopant regions PR is together formed as a region (secondp-type dopant region) from which source electrodes S are taken out. Thedrain electrode D, the dopant region from which the source electrodes Sare taken out, and gate electrodes G constitute p-type transistors PTRas the high-breakdown-voltage pMOSFET. In FIG. 2, therefore, the p-typetransistors PTR are illustrated in a number of two. The two p-typetransistors PTR have the following members commonly to each other: thedrain electrode D; the p-type dopant region PR from which the drainelectrode D is taken out; and the high-breakdown-voltage p-type driftHPDF.

The respective gate electrodes G of the two p-type transistor PTR areeach composed of a gate insulating film GI that is, for example, asilicon oxide film, a gate voltage applying region GE to which a voltageis applied, and a side wall insulating film SW that is, for example, asilicon oxide film.

In the main surface MS of the semiconductor substrate SUB, the n-typewell region LNW is formed. In a region of the main surface MS which is aregion where the n-type well region LNW is formed, partly, the followingmembers are formed: the p-type dopant region PR from which the sourceelectrodes S are taken out; and the n-type dopant region NR from whichbase potential B is taken out. In other words, the n-type well regionLNW is formed in the main surface MS to surround the periphery of thep-type dopant region PR from which the source electrodes S are takenout, and that of the n-type dopant region NR from which the basepotential B is taken out. In the same manner as introduced into then-type buried layer NI, ions of an n-type dopant are introduced into then-type well region LNW and the n-type dopant region NR.

The n-type dopant region NR, from which the base potential B is takenout, has a function of connecting the base potential B electrically withthe n-type well region LNW, thereby fixing the potential of the n-typewell region LNW. As illustrated in FIG. 3, it is preferred that then-type dopant region NR, from which the base potential B is taken out,is arranged, for example, to surround the (paired) p-type transistorsPRT when these are viewed in plan.

It is preferred that the n-type well region LNW is arranged to includeat least one portion of a region just below each of the gate electrodesG. According to this manner, in the main surface MS and the n-type wellregion LNW near the main surface MS, a channel region causing anelectric field effect of each of the p-type transistors PTR is formed,in particular, in at least one portion of a region sandwiched betweenits drain electrode D and its source electrode S. This electric fieldeffect is caused by a voltage applied to the gate electrode G (gatevoltage applying region GE) just above the channel.

The element isolation insulating film LS is an insulating film formedas, for example, a silicon oxide film on/in, for example, at least oneportion of a region sandwiched between the base potential B and thesource electrode S, this region being a region of the main surface MS,in order to isolate the p-type transistors PTR, which are adjacent onesout of all p-type transistors in the present device. The elementisolation film LS is formed through, for example, the so-called LOCOS(local oxidation of silicon) process or STI (shallow trench isolation)process.

The element isolating insulating film LS is preferably formed in, forexample, at least one portion (for example, a portion just below theside wall insulating film SW) of a region sandwiched between the gateelectrode G of each of the p-type transistors PTR and the drainelectrode D thereof, this region being a region of the main surface MS.The element isolation insulating film LS formed in this region restrainsthe generation of a portion extremely low in dopant concentration in thechannel region of the p-type transistor PTR, which is formed in, forexample, the main surface MS of the n-type well region LNW and thevicinity of the main surface MS by ion implantation. This portion, lowin dopant concentration, may cause a fall in the electric field effectto induce an inconvenience that the threshold voltage of the gateelectrode G becomes very high. Thus, when the element isolationinsulating film LS is formed in a portion that may, with a highprobability, become this portion, which is low in dopant concentration,a portion high in threshold voltage is substantially extinguished justbelow the gate electrode G to make it possible to restrain thegeneration of inconveniences, such as respective falls in the draincurrent of the high-breakdown-voltage pMOSFET and in the reliabilitythereof.

In the meantime, the high-breakdown-voltage nMOSFET mainly has an n-typeburied layer NI (second n-type semiconductor layer), an n-type wellregion LNW, a p-type well region LPW, low-concentration n-type regionsNNR, n-type dopant regions NR, a p-type dopant region PR, gateelectrodes G, and an element isolation insulating film LS. These areformed in the semiconductor substrate SUB, which has the same p-typeregion PSR where the high-breakdown-voltage pMOSFET is formed. In thesame manner as introduced into the p-type region PSR and the others,p-type dopant ions are introduced into the p-type well region LPW. Inthe same manner as introduced into the n-type dopant regions NR and theothers, n-type dopant ions are introduced into the low-concentrationn-type regions NNR.

A p-type region PSR of the high-breakdown-voltage nMOSFET, and then-type buried layer NI thereof are common to those of thehigh-breakdown-voltage pMOSFET, respectively. In other words, the p-typeregion PSR of the high-breakdown-voltage nMOSFET, and that of thehigh-breakdown-voltage pMOSFET are present as the same layer, andfurther the n-type buried layer NI of the high-breakdown-voltage nMOSFETand that of the high-breakdown-voltage pMOSFET are present as the samelayer.

A region from which drain electrodes D are taken out is made of one ofthe n-type dopant regions NR that is formed in the nMOSFET-side mainsurface MS of the semiconductor substrate SUB, and one of thelow-concentration n-type regions NNR that is formed to surround theperiphery of this region NR. It is preferred that the concentration ofthe n-type dopant in the low-concentration n-type region NNR is higherthan that of the n-type dopant in the n-type well region LNW, and islower than that of the n-type dopant in the n-type dopant region NR.Even when a high voltage is applied to the drain electrodes D, thestructure described herein makes it possible to restrain the generationof inconveniences following a matter that an electric field becomesextremely high in the n-type dopant region NR and the vicinity thereof.A region from which source electrodes S are taken out may also have ann-type dopant region NR (as the other of the n-type dopant regions) anda low-concentration n-type region NNR (as the other of thelow-concentration n-type regions NNR) formed to surround the peripheryof the region NR.

The drain electrodes D, the dopant region from which the sourceelectrodes S are taken out, and the gate electrodes G constitute n-typetransistors NTR as the high-breakdown-voltage nMOSFET.

Furthermore, the p-type dopant region PR, from which the base potentialB is taken out, has a function of connecting the base potential B andthe p-type well region LPW electrically with each other to fix thepotential of the p-type well region LPW.

The local n-type buried region RBN is a region in thehigh-breakdown-voltage pMOSFET which is a region arranged just below thefirst p-type dopant region from which the drain electrode D is takenout, that is, a region arranged at the p-type region PSR side of thefirst p-type dopant region. It is preferred that this local n-typeburied region RBN is arranged just below the first p-type dopant region,particularly just below the p-type dopant region PR therein. It ishowever allowable that this region RBN is just below both of the p-typedopant region PR and the high-breakdown-voltage p-type drift layer HPDF,which constitute the first p-type dopant region.

As described above, the local n-type buried region RBN may be arrangedto include a region just below the first p-type dopant region, fromwhich the drain electrode D is taken out, or may be arranged to make thecircumference thereof consistent with that of first p-type dopant regionwhen viewed in plan (for example, this region RBN has the same planesurface shape as the first p-type dopant region so as to be laidunderneath the first p-type region with substantially completelyconsistence in shape with the first p-type dopant region). The localn-type buried region RBN may be arranged to have the same plane surfaceshape as, in particular, the p-type dopant region PR in the first p-typedopant region, or may be arranged to have the same plane surface shapeas a region made of a combination of the p-type dopant region PR and thehigh-breakdown-voltage p-type drift layer HPDF, which constitute thefirst p-type dopant region (that is, a region which is identical inshape to the high-breakdown-voltage p-type drift layer HPDF when viewedin plan).

The transverse axis (depth) of a graph of FIG. 4 represents the relativequantity of the distance of any position in the vertical direction inFIG. 2 from the main surface MS of the semiconductor substrate SUBinside the semiconductor substrate SUB in FIG. 2. The vertical axis(concentration) of the graph of FIG. 4 represents the relative quantityof the concentration of the dopant (boron in the p-type dopant region orphosphorous in the n-type dopant region) in this depth-region.

The local n-type buried region RBN in FIG. 2 is defined as a regionwhere the concentration of phosphorous, which is a dopant, introducedfor forming this region RBN is higher than not only that of the dopantintroduced for forming any one of the other regions (for example,phosphorous for forming the n-type buried layers NI, or boron forforming the high-breakdown-voltage p-type drift layer HPDF), but alsothe concentration of the p-type dopant in the p-type region PSR.Similarly, the high-breakdown-voltage p-type drift layer HPDF in FIG. 2is defined as a region where the concentration of boron for forming thislayer HPDF is higher than that of the dopant for forming any one of theother regions (including the p-type region PSR). The n-type buriedlayers NI in FIG. 2 are each defined as a region where the concentrationof phosphorous for forming this layer is higher than that of the dopantfor forming any one of the other regions (including the p-type regionPSR).

As shown in FIGS. 2 and 4, in the present embodiment, the local n-typeburied region RBN is arranged at the main surface MS side, that is, theupside (in FIG. 2) of one of the n-type buried layers NI (i.e., at theleft side of an NI-corresponding position in FIG. 4). In the embodiment,a position where the phosphorous concentration in the local n-typeburied region RBN becomes maximum is arranged, in particular, at themain surface MS side, that is, the upside (in FIG. 2) of a positionwhere the phosphorous concentration in the n-type buried layer NIbecomes maximum, and is further arranged at the p-type region PRS side,that is, the downside (in FIG. 2) of a position where the boronconcentration in the high-breakdown-voltage p-type drift layer HPDFbecomes maximum. In FIG. 4, the maximum dopant concentration in thelocal n-type buried region RBN is substantially equal to that in then-type buried layer NI; however, the maximum dopant concentration in thelocal n-type buried region RBN may be higher than that in the n-typeburied layer NI.

The local n-type buried region RBN is arranged to contact the n-typeburied layer NI. In other words, as illustrated in FIG. 4, theconcentration profile of the local n-type buried region RBN meets thatof the n-type buried layer NI while as illustrated in FIG. 2, thepresent device does not include, between the local n-type buried regionRBN and the n-type buried region NI, the other regions, such as thep-type region PSR.

As illustrated in the sectional view of FIG. 2, it is preferred that thelocal n-type buried region RBN is formed to contact the n-type wellregion LNW arranged, in the direction along the main surface MS, at bothsides of the local n-type buried region RBN. In another wording, asillustrated in the sectional view of FIG. 2, it is preferred that thelocal n-type buried region RBN is arranged so as to be coupled to then-type well region LNW portions or sections adjacent to each other, inthe direction along the main surface MS, to the region RNB (i.e., so asto bridge the portions or sections of the n-type well region LNW). Thelocal n-type buried region RBN attains connection between the n-typewell region LNW portions or sections, the portions or sections beingarranged oppositely to each other (at the right and left sides of thehigh-breakdown-voltage p-type drift layer HPDF in FIG. 2) across thefirst p-type dopant region (high-breakdown-voltage p-type drift layerHPDF) in the direction along the main surface MS. In still anotherwording, it is preferred that the n-type well region LNW surrounds thelocal n-type buried region RBN to contact this local n-type buriedregion RBN. The n-type well region LNW may surround the local n-typeburied region RBN to contact the first p-type dopant region(high-breakdown-voltage p-type drift layer HPDF).

With reference to FIGS. 5 to 14, a description will be made about amethod for producing the semiconductor device of the embodiment.

As illustrated in FIG. 5, prepared is first a semiconductor substrateSUB made of silicon monocrystal and having, for example, a p-type regionPSR containing therein a p-type dopant. An ordinary photolithography(light exposure technique and development technique) is used to form,onto one MS of the two main surfaces of the semiconductor substrate SUB,a pattern of a photoresist PHR where openings are made in regions wherean element isolation insulating film LS is to be formed when thephotoresist PHR is viewed in plan.

As illustrated in FIG. 6, for example, through an ordinary LOCOS or STIprocess, the element isolation insulating film LS (described just above)which is, for example, a silicon oxide film is formed in regions of themain surface MS which correspond to the openings in the photoresist PHR.

Next, the photoresist PHR is removed, and then a silicon oxide filmhaving a thickness of, for example, 10 to 50 nm both inclusive is formedon substantially the whole of the main surface MS, which step is notillustrated. Referring again to FIG. 6, next, an ordinaryphotolithography is used to form a pattern of a photoresist PHR whereinan opening is made in a region where a high-breakdown-voltage p-typedrift layer HPDF is to be formed when the photoresist PHR is viewed inplan.

As illustrated in FIG. 7, by an ordinary ion implantation method, dopantions of, for example, boron (B) are implanted plural times, at an energyof 50 to 300 keV both inclusive, into the main surface MS from above thesurface MS. As a result, the high-breakdown-voltage p-type drift layerHPDF (described just above) is formed. Subsequently, by an ionimplantation method, dopant ions of phosphorous (P) are implanted, at anenergy of 500 keV to 2 MeV both inclusive, into the main surface MS fromabove the surface MS. As a result, a local n-type buried region RBN isformed.

Next, removed is the photoresist PHR (used to form thehigh-breakdown-voltage p-type drift layer HPDF and the local n-typeburied region RBN), and then an ordinary photolithography is used toform a pattern of a photoresist PHR where openings are made in regionswhere n-type buried layers NI are to be formed when the photoresist PHRis viewed in plan.

As illustrated in FIG. 8, by an ion implantation method, dopant ions of,for example, phosphorous (P) are implanted, at energy of 1 to 5 MeV bothinclusive, into the main surface MS from above the surface MS. As aresult, the n-type buried layers NI (described just above) are formedinside the semiconductor substrate SUB and at the main surface MS side(the upside) of the p-type region PSR. The n-type buried layers NIformed simultaneously in this step are: an n-type buried layer NI (firstn-type semiconductor layer) in a high-breakdown-voltage pMOSFET region;and an n-type buried layer NI (second n-type semiconductor layer in ahigh-breakdown-voltage nMOSFET region.

Next, removed is the photoresist PHR (used to the n-type buried layersNI), and then an ordinary photolithography is used to form a pattern ofa photoresist PHR where openings are made in a region where an n-typewell region LNW is to be formed when the photoresist PHR is viewed inplan.

As illustrated in FIG. 9, by an ion implantation method, dopant ions of,for example, phosphorous (P) are implanted, at an energy of 150 to 2000keV both inclusive, into the main surface MS from above the surface MSand further dopant ions of boron (B) are implanted, at an energy of 20to 50 keV both inclusive, into the same. As a result, the n-type wellregion LNW (described just above) is formed.

Next, removed is the photoresist PHR (used to form the n-type wellregion LNW), and then an ordinary photolithography is used to form apattern of a photoresist PHR where openings are made in a region where ap-type well region LPW is to be formed when the photoresist PHR isviewed in plan.

As illustrated in FIG. 10, by an ion implantation method, dopant ionsof, for example, boron (B) are implanted, at an energy of 20 to 1000 keVboth inclusive, into the main surface MS from above the surface MS. As aresult, the p-type well region LPW (described just above) is formed.

Next, removed is the photoresist PHR (used to form the p-type wellregion LPW), and then removed is the silicon oxide film formedpreviously on substantially the whole of the main surface MS. Next, anordinary thermal oxidation method is used to form an insulating film(GI) (i.e., a silicon oxide film having a thickness of 10 to 50 nm bothinclusive) for forming a gate insulating film GI. An ordinary CVD(chemical vapor deposition) method is used to form a polycrystal siliconfilm (GE) for forming gate voltage applying regions GE.

Furthermore, an ordinary photolithography is used to form, on thepolycrystal silicon film (GE), a pattern of a photoresist PHR whereinopenings are made in regions where the insulating film (GI) and thepolycrystal silicon film (GE) are to be removed when the photoresist PHRis viewed in plan.

As illustrated in FIG. 11, the photoresist PHR pattern in FIG. 10 isused as a photomask to etch the insulating film (GI) and the polycrystalsilicon film (GE) in an ordinary manner to form a gate insulating filmas the film GI, and gate voltage applying regions as the regions GE.

Next, removed is the photoresist PHR (used to form the gate insulatingfilm GI and the other), and then an ordinary photolithography is used toform a pattern of a photoresist PHR wherein openings are made in notonly regions where low-concentration n-type regions NNR are to be formedwhen the photoresist PHR is viewed in plan, but also regions which aresuperposed on the gate voltage applying regions GE when the photoresistPHR is viewed in plan.

As illustrated in FIG. 12, by an ordinary ion implantation method,dopant ions of, for example, phosphorous (P) are implanted, at an energyof 50 to 200 keV both inclusive, into the main surface MS from above thesurface MS. As a result, the low-concentration n-type regions NNR(described just above) are formed.

Next, removed is the photoresist PHR (used to form the low-concentrationn-type regions NNR), and then a silicon oxide film is deposited ontosubstantially the whole of the main surface MS by, for example, a CVDmethod to cover the upper surfaces of the gate voltage applying regionsGE and so on. The thickness of this silicon oxide film is preferablyfrom 30 to 300 nm both inclusive. Thereafter, the silicon oxide film isetched back, thereby forming a side wall insulating film SW to coverside surfaces of the gate voltage applying regions GE and the gateinsulating film GI. Through the steps described hereinbefore, gateelectrodes G are formed.

As illustrated in FIG. 13, an ordinary photolithography is used to forma pattern of a photoresist PHR wherein openings are made in regionswhere n-type dopant regions NR are to be formed when the photoresist PHRis viewed in plan.

As illustrated in FIG. 14, by an ion implantation method, dopant ionsof, for example, arsenic (As) are implanted, at an energy of 30 to 70keV both inclusive, into the main surface MS from above the surface MS.As a result, the n-type dopant regions NR (described just above) areformed. In this way, formed are an (n-type) dopant region from whichdrain electrodes D and source electrodes S of the high-breakdown-voltagenMOSFET are taken out, and an (n-type) dopant region from which the basepotential B of the high-breakdown-voltage pMOSFET is taken out.

Furthermore, removed is the photoresist PHR (used to form the n-typedopant regions NR), and then an ordinary photolithography is used toform a pattern of a photoresist PHR wherein openings are made in regionswhere p-type dopant regions PR are to be formed when the photoresist PHRis viewed in plan. Thereafter, by an ion implantation method, dopantions of, for example, boron fluoride (BF₂) are implanted, at an energyof 20 to 60 keV both inclusive, into the main surface MS from above thesurface MS. As a result, referring again to FIG. 2, the p-type dopantregions PR (described just above) are formed. In this way, formed are a(p-type) dopant region from which a drain electrode D and sourceelectrodes S of the high-breakdown-voltage pMOSFET are taken out, and a(p-type) dopant region from which the base potential B of thehigh-breakdown-voltage nMOSFET is taken out. As a result, p-typetransistors PTR and n-type transistors NTR are formed.

Just after each of the above-mentioned ion implantation methods is usedto implant the dopant concerned, thereby forming the region concerned,the semiconductor substrate SUB is subjected to an ordinary thermaltreatment to make the formed region into a stable state. Through each ofthe above-mentioned steps, the high-breakdown-voltage pMOSFET and thehigh-breakdown-voltage nMOSFET are formed, and simultaneously individualconstituents of MOSFETs which constitute the low-voltage logic circuitand the others in FIG. 1 are also formed, which situation is notillustrated in any one of the figures.

The following will describe the effect and advantages of the presentembodiment with reference to FIG. 15 illustrating a technique related tothe embodiment.

As illustrated in FIG. 15, in the same manner as illustrated in FIG. 2,a region where a high-breakdown-voltage analogue I/O circuit as thetechnique related to the embodiment is formed has ahigh-breakdown-voltage pMOSFET and a high-breakdown-voltage nMOSFET. InFIG. 15, however, just below a p-type dopant region PR from which adrain electrode D of each p-type transistor PTR is taken out, no localn-type buried region RNB is arranged. The structure in FIG. 15 isdifferent in this point from that illustrated in FIG. 2. However, inother points, the structure in FIG. 15 is equal to that in FIG. 2; thus,in FIG. 15, to the same constituting elements as in FIG. 2 are attachedthe same reference symbols, respectively. The description of the sameelements is not repeated.

In the structure in FIG. 15, in the same way as in the presentembodiment, the n-type buried layer NI, the n-type well region LNW, thehigh-breakdown-voltage p-type drift layer HPDF, and the others are eachformed by an ion implantation method. In this case, therefore, costs forthe production can be made lower than, for example, in the case offorming semiconductor layers by epitaxial growth as described in theabove-mentioned publication (Patent Document 1).

As has been illustrated in FIG. 15, however, in this structure, aparasite pnp bipolar transistor may be generated among thehigh-breakdown-voltage p-type drift layer HPDF, the n-type buried layerNI just below the layer HPDF, and the p-type region PSR just below thelayer NI, which are arranged in the vertical direction in FIG. 15. Inparticular, in a case where a reverse regenerative current flows from amotor or some other into the region from which the drain electrode D istaken out, the following probability is caused when this parasite pnpbipolar transistor acts: the reverse regenerative current partiallyflows as a leakage current toward the p-type region PSR (semiconductorsubstrate SUB) corresponding to the connector of the bipolar transistorso that elements around the present MOSFET malfunction, or the p-typetransistors PTR are thermally broken.

In order to restrain the leakage current flowing toward the p-typeregion PSR (downward in FIG. 15), it is preferred to increase the dopantconcentration in the n-type buried layer NI, which acts the base of thebipolar transistor, or increase the thickness (in the vertical directionin FIG. 15) of the n-type buried layer NI. This manner can be realizedby increasing the dosage of ions implanted into the n-type buried layerNI, or apply multistep-implantation to the n-type buried layer NI.However, when this processing is applied to the structure in FIG. 15,the action of a parasite npn bipolar transistor is promoted although theeffect of the parasite transistor onto each of the p-type transistorsPTR is decreased; the parasite npn bipolar transistor is generated amongthe n-type dopant region NR and the low-concentration n-type region NNR,from which the source electrodes of the n-type transistors NTR are takenout, the p-type well region LPW just below the region NNR, and then-type buried layer NI just below the region LPW. This is because then-type dopant concentration in the n-type buried layer NI as the emitterof the npn bipolar transistor becomes high, or the n-type buried layerNI becomes thick. Since the parasite bipolar transistor of the n-typetransistors NTR acts easily, the parasite transistor may cause theelements to malfunction in the same manner as described above.

The problems described just above can be solved, for example, byincreasing the thickness of only the n-type buried layer NI of thep-type transistors PTR or by increasing the dopant concentrationtherein. However, in order to attain this manner, it is necessary toprepare one photomask additionally. Thus, the production costs may beincreased.

Thus, as attained in the present embodiment (FIG. 2), the local n-typeburied region RBN is arranged to contact the n-type buried layer NI,thereby increasing the n-type dopant region, as the base, substantiallyin thickness in the region where the parasite pnp bipolar transistoracts easily in FIG. 15. For this reason, in this region, the parasitepnp bipolar transistor comes not to act easily. Accordingly, thesemiconductor device of the present embodiment makes it possible torestrain malfunctions of the peripheral circuit that are caused by theaction of the parasite bipolar transistor, and thermal breaking of thep-type transistors PTR. This advantageous effect is further increasedwhen the local n-type buried layer RBN is arranged at a position justbelow the region from which the drain electrode D of thehigh-breakdown-voltage p-type transistors PTR is taken out (the region:the p-type dopant region PR and the high-breakdown-voltage p-type driftlayer HPDF) (i.e., a position where the circumference of the layer RBNis made consistent with that of the region from which the drainelectrode D is taken out when the semiconductor device is viewed inplan) to have the same two-dimensional shape as the region from whichthe drain electrode D is taken out. This is because the parasite bipolartransistor is formed by a matter that the p-type region, the n-typeregion and the p-type region are arranged in turn along the verticaldirection in FIG. 2.

The local n-type buried region RBN in the present embodiment is veryadvantageously usable particularly when a semiconductor device has ahigh-breakdown-voltage pMOSFET and a high-breakdown-voltage nMOSFET andfurther these MOSFETs have the same layer (the n-type buried layer NI inthis embodiment) in common. This is because as described above, the formof the present embodiment is adopted in order to avoid an inconvenience(the promotion of the action of a parasite npn bipolar transistor) thatmay be caused in the high-breakdown-voltage nMOSFET by increasing theconcentration of the n-type dopant in the n-type buried layer NI of thehigh-breakdown-voltage nMOSFET and the thickness of the n-type buriedlayer NI.

In the present embodiment, the local n-type buried region RBN isarranged to be coupled to portions or sections of the n-type well regionthat are arranged (at the right and left sides of thehigh-breakdown-voltage p-type drift layer HPDF in FIG. 2) to beopposite, in a direction along the main surface MS, to each other acrossthe high-breakdown-voltage p-type drift layer HPDF. Therefore, forexample, the p-type region PSR contacting the lower side of thehigh-breakdown-voltage p-type drift layer HPDF in FIG. 2 does not causeany connection between the high-breakdown-voltage p-type drift layerHPDF and the n-type buried layer NI. It is therefore possible torestrain the flowing of a leakage current into between thehigh-breakdown-voltage p-type drift layer HPDF and the n-type buriedlayer NI just below the layer HPDF (a current flowing from thehigh-breakdown-voltage p-type drift layer HPDF toward the n-type buriedlayer NI when a reverse regenerative current flows into the drainregion). Thus, it is possible to restrain thermal breaking of the p-typetransistors PTR and malfunctions of the peripheral circuit.

As attained in the present embodiment, the local n-type buried regionRBN is present nearer to the main surface MS than the n-type buriedlayer NI is, thereby making it possible to make the distance shorterbetween the high-breakdown-voltage p-type drift layer HPDF and then-type buried layer NI just below the layer HPDF. As a result, it istherefore possible to restrain the flowing of a leakage current intobetween the high-breakdown-voltage p-type drift layer HPDF and then-type buried layer NI just below the layer HPDF (a current flowing fromthe high-breakdown-voltage p-type drift layer HPDF toward the n-typeburied layer NI when a reverse regenerative current flows into the drainregion). Thus, it is possible to restrain thermal breaking of the p-typetransistors PTR and malfunctions of the peripheral circuit.

Furthermore, in the method for producing the present embodiment, thesame photomask is used to form the high-breakdown-voltage p-type driftlayer HPDF and the local n-type buried region RBN (continuously alongtime) to make it possible to reduce time and costs required for theproduction process. As described above, the local n-type buried regionRBN and the high-breakdown-voltage p-type drift layer HPDF have the sametwo-dimensional shape, and further the local n-type buried region RBN isarranged just below the high-breakdown-voltage p-type drift layer HPDFto make the circumferences of the two completely consistent with eachother when viewed in plan. Thus, using the same photomask, the localn-type buried region RBN and the high-breakdown-voltage p-type driftlayer HPDF can easily be formed.

Herein, the present embodiment is compared with the prior art. In, forexample, the technique of the above-mentioned publication, it isnecessary to use separately one photomask exclusive to the formation ofa buried layer. Furthermore, a thin film is formed by epitaxial growthto cover the buried layer; thus, much time and large costs are requiredfor the production process. In the present embodiment, however, thelocal n-type buried region RBN can be formed, using a photomask forforming the high-breakdown-voltage p-type drift layer HPDF. Thus, itbecomes unnecessary to prepare a photomask separately as performed inthe publication, whereby time and costs required for the productionprocess are largely reduced.

The technique of using, in this way, the same photomask as used for thehigh-breakdown-voltage p-type drift layer HPDF to form the local n-typeburied region RBN can be realized by forming the local n-type buriedregion RBN just below the high-breakdown-voltage p-type drift layer HPDFto make the circumferences of the two completely consistent with eachother (the two are made into the same two-dimensional shape) when viewedin plan.

Second Embodiment

The local n-type buried region RBN formed by ion implantation in thestep illustrated in FIG. 7 can, with a higher certainty, restrain theaction of a parasite bipolar transistor in the high-breakdown-voltagepMOSFET (p-type transistors PTR) and a leakage current, which followsthe action, into the p-type region PSR (substrate leakage current) byvarying conditions for forming the region RBN.

Specifically, the action and leakage current described just above can berestrained with a higher certainty, for example, by lowering the energyfor the ion implantation for forming the local n-type buried region RBN,or increasing the dosage of the implanted ions.

The transverse axis of FIG. 16A represents the magnitude of energy forion implantation (for forming, for example, the local n-type buriedregion RBN), and the ordinate axis represents the proportion of thesubstrate leakage current of one of the p-type transistors PTR, and themagnitude of the breakdown voltage thereof. The substrate leakagecurrent denotes the following out of components of a current flowinginto the p-type dopant region PR from which the drain electrode is takenout when the motor or the like turns into a reverse regenerative state:a current component leaking through the parasite bipolar transistor ofthe p-type transistor PTR to the p-type region PSR of the semiconductorsubstrate SUB.

As illustrated in 16A, as the ion implantation energy is made lower, thelocal n-type buried region RBN in the p-type transistor PTR becomesthicker. As a result, the region functioning as the base of the parasitebipolar transistor of the p-type transistor PTR becomes thicker. Thus,the function of the p-type transistor PTR as the bipolar transistor isdeteriorated so that the proportion of the substrate leakage current canbe lowered.

The transverse axis of FIG. 16B represents the dosage of ionimplantation (for forming, for example, the local n-type buried regionRBN), and the ordinate axis represents the proportion of the substrateleakage current of one of the p-type transistors PTR, and the magnitudeof the breakdown voltage thereof.

As illustrated in 16B, as the ion implantation dosage is made larger,the dopant concentration in the local n-type buried region RBN in thep-type transistor PTR becomes higher. As a result, the regionfunctioning as the base of the parasite bipolar transistor of the p-typetransistor PTR becomes higher in dopant concentration. Thus, thefunction of the p-type transistor PTR as the bipolar transistor isdeteriorated so that the proportion of the substrate leakage current canbe lowered.

As has been shown in FIGS. 16A and 16B, in each of the case where theion implantation energy is decreased and that where the ion implantationdosage is increased, the breakdown voltage of the p-type transistor PTRis declined. It is therefore desired to adjust the ion implantationenergy and the ion implantation dosage in accordance with aspecification required for the p-type transistor PTR.

The structural features of the present embodiment may be appropriatelycombined with those of first embodiment.

Third Embodiment

As illustrated in FIG. 17, a region where a high-breakdown-voltageanalogue I/O circuit is formed in the present embodiment basically hasthe same structure as the region where the high-breakdown-voltageanalogue I/O circuit is formed in first embodiment illustrated in FIG.2. In the present embodiment, however, a local n-type buried region RBNis arranged at a side of an n-type buried layer NI opposite to themain-surface-MS-side of the layer NI, that is, the downside of the layerNI in FIG. 2 (i.e., at the right side of the NI-corresponding positionin FIG. 4) to contact the n-type buried layer NI. Accordingly, the localn-type buried region RBN in the present embodiment is arranged to besurrounded by (or embedded in) a p-type region PSR of a semiconductorsubstrate SUB.

In the present embodiment also, a desired semiconductor device is formedby a producing method basically equivalent to the method described infirst embodiment (see FIGS. 5 to 14). In the present embodiment,however, in the step illustrated in FIG. 7 for first embodiment, it ispreferred to set, into the range of 2.6 to 5 MeV both inclusive, theenergy for implanting dopant ions of phosphorous (P) when the localn-type buried region RBN is formed. In this way, the local n-type buriedregion RBN is formed at a region deeper than the region-RBN-formedregion in FIG. 7 illustrating first embodiment.

In this point, the structure in FIG. 17 is different from that in FIG.2. However, in other points, the structure in FIG. 17 is equal to thatin FIG. 2; thus, in FIG. 17, to the same constituting elements as inFIG. 2 are attached the same reference symbols, respectively. Thedescription of the same elements is not repeated.

The following will describe the effect and advantages of the presentembodiment. The embodiment produces the following effect and advantagesbesides those of first embodiment.

When the present embodiment is compared with first embodiment, the localn-type buried region RBN is arranged at a region farther (deeper) fromthe main surface MS. Accordingly, the local n-type buried region RBN inthe present embodiment is higher in ion implantation energy (shown inFIG. 16A), in the formation of the region RBN, than the local n-typeburied region RBN in first embodiment. As has been shown in the graph ofFIG. 16A, therefore, the p-type transistors PTR in the presentembodiment are made larger in breakdown-voltage-improving effect thanthose in first embodiment.

The structural features of the present embodiment may be appropriatelycombined with those of first embodiment and/or second embodiment.

Fourth Embodiment

As illustrated in FIG. 18, a region where a high-breakdown-voltageanalogue I/O circuit is formed in the present embodiment basically hasthe same structure as the region where the high-breakdown-voltageanalogue I/O circuit is formed in first embodiment illustrated in FIG.2. In the present embodiment, however, a local n-type buried region RBNis arranged inside an n-type buried layer NI. Accordingly, just belowp-type dopant regions PR of a drain electrode D (and ahigh-breakdown-voltage p-type drift layer HPDF), the local n-type buriedregion RBN in the present embodiment is arranged in the same regionwhere the n-type buried layer NI is formed.

In this case, a region where the dopant concentration is made largest bythe local n-type buried region RBN is present inside the n-type buriedlayer NI. In other words, the region where the dopant concentration ismade largest is present at the same position (same coordinates), aboutthe vertical direction in FIG. 18, where the n-type buried layer NI ispresent.

In the present embodiment also, a desired semiconductor device is formedby a producing method basically equivalent to the method described infirst embodiment (see FIGS. 5 to 14). In the present embodiment,however, in the step illustrated in FIG. 7 for first embodiment, it ispreferred to set, into the range of, for example, 2 to 3.5 MeV bothinclusive, the energy for implanting dopant ions of phosphorous when thelocal n-type buried region RBN is formed; any energy in the rangedescribed just above is equivalent to the ion implantation energy whenthe n-type buried layer NI is formed. In this way, the local n-typeburied region RBN is formed at a region deeper than theregion-RBN-formed region in FIG. 7 illustrating first embodiment. Inthis way, the local n-type buried region RBN is formed in a regiondeeper than the region-RBN-formed region in FIG. 7 for first embodimentand shallower than that in FIG. 17 for third embodiment.

In this point, the structure in FIG. 18 is different from that in FIG.2. However, in other points, the structure in FIG. 18 is equal to thatin FIG. 2; thus, in FIG. 18, to the same constituting elements as inFIG. 2 are attached the same reference symbols, respectively. Thedescription of the same elements is not repeated.

The following will describe the effect and advantages of the presentembodiment. As described above, in the embodiment, the local n typeburied region RBN is formed at the same position where the n-type buriedlayer NI is formed. However, when the dopant concentration profilethereof is considered, the formation of the local n type buried regionRBN increases the thickness of the n-type dopant region just below theregion where the drain electrodes are taken out, and the concentrationof the n-type dopant in this region as this case is compared with a casewhere the local n type buried region RBN is not present. For thisreason, the local n type buried region RBN in the present embodimentproduces the same effect and advantages as the other embodiments.

The structural features of the present embodiment may be appropriatelycombined with those of first embodiment, second embodiment and/or thirdembodiment.

The above has specifically described the invention made by the inventorsby way of the embodiments of the invention. However, the presentinvention is not limited into the embodiments, and may be, of course,modified into various forms as far as the modified embodiments do notdepart from the subject matter of the invention.

What is claimed is:
 1. A method for producing a semiconductor devicecomprising a semiconductor substrate having a main surface and furtherhaving, in an internal region thereof, a p-type region, and ahigh-breakdown-voltage p-channel-type transistor in the semiconductorsubstrate, wherein a step in which the high-breakdown-voltagep-channel-type transistor is formed comprises: preparing thesemiconductor device, which comprises the semiconductor substrate havingthe main surface and further having, in the internal region thereof, thep-type region; forming a first n-type semiconductor layer inside thesemiconductor substrate and at the main-surface-side of the p-typeregion; forming a first p-type dopant for taking out a drain electrodeover the p-type region and in/on the main surface; forming a secondp-type region for taking out a source electrode over the p-type regionand in/on the main surface; and forming a local n-type buried regionjust below the first p-type dopant region to contact the first n-typesemiconductor layer, wherein the same mask is used to conduct the stepof forming the first p-type dopant region and the step of forming thelocal n-type buried region.
 2. The method for producing a semiconductordevice according to claim 1, wherein the semiconductor substrate furthercomprises a high-breakdown-voltage n-channel-type transistor comprisinga second n-type semiconductor layer as a layer identical to the firstn-type semiconductor layer of the high-breakdown-voltage p-channel-typetransistor, and a step of forming the second n-type semiconductor layerof the high-breakdown-voltage n-channel-type transistor is performedsimultaneously with the step of forming the first n-type semiconductorlayer of the high-breakdown-voltage p-channel-type transistor.
 3. Themethod for producing a semiconductor device according to claim 2,wherein the local n-type buried region is formed by an ion implantationmethod.
 4. The method for producing a semiconductor device according toclaim 2, wherein the first p-type dopant region is formed by an ionimplantation method.
 5. The method for producing a semiconductor deviceaccording to claim 2, wherein the first n-type semiconductor layer isformed by an ion implantation method.